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Silicon Labs /SiM3_NRND /SIM3L164_C /PMU_0 /CONTROL

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Interpret as CONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLEAR)WAKECLR 0 (DISABLED)PWAKEEN 0 (DISABLED)PMUASLPEN 0 (DISABLED)CPMONEN 0 (DISABLED)CPMONIEN 0 (DISABLED)RAM0REN 0 (DISABLED)RAM1REN 0 (DISABLED)RAM2REN 0 (DISABLED)RAM3REN 0 (DISABLED)RAM4REN 0 (DISABLED)RAM5REN 0 (DISABLED)RAM6REN 0 (DISABLED)RAM7REN

RAM0REN=DISABLED, CPMONEN=DISABLED, PWAKEEN=DISABLED, CPMONIEN=DISABLED, WAKECLR=CLEAR, RAM2REN=DISABLED, RAM5REN=DISABLED, PMUASLPEN=DISABLED, RAM1REN=DISABLED, RAM4REN=DISABLED, RAM7REN=DISABLED, RAM6REN=DISABLED, RAM3REN=DISABLED

Description

Module Control

Fields

WAKECLR

Wakeup Source Clear.

0 (CLEAR): Clear all wakeup sources.
PWAKEEN

Pin Wake Match Enable.

0 (DISABLED): Disable Pin Wake.

1 (ENABLED): Enable Pin Wake.
PMUASLPEN

PMU Asleep Pin Enable.

0 (DISABLED): Disable the PMU Asleep pin.

1 (ENABLED): Enable the PMU Asleep pin.
CPMONEN

Low Power Charge Pump Voltage Monitor Enable.

0 (DISABLED): Disable the low power charge pump voltage monitor.

1 (ENABLED): Enable the low power charge pump voltage monitor.
CPMONIEN

Low Power Charge Pump Voltage Monitor Interrupt Enable.

0 (DISABLED): Disable the low power charge pump voltage monitor interrupt.

1 (ENABLED): Enable the low power charge pump voltage monitor interrupt.
RAM0REN

RAM 0 Retention Enable.

0 (DISABLED): Disable power to RAM 0 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 0 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).
RAM1REN

RAM 1 Retention Enable.

0 (DISABLED): Disable power to RAM 1 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 1 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).
RAM2REN

RAM 2 Retention Enable.

0 (DISABLED): Disable power to RAM 2 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 2 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).
RAM3REN

RAM 3 Retention Enable.

0 (DISABLED): Disable power to RAM 3 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 3 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).
RAM4REN

RAM 4 Retention Enable.

0 (DISABLED): Disable power to RAM 4 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 4 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).
RAM5REN

RAM 5 Retention Enable.

0 (DISABLED): Disable power to RAM 5 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 5 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).
RAM6REN

RAM 6 Retention Enable.

0 (DISABLED): Disable power to RAM 6 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 6 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).
RAM7REN

RAM 7 Retention Enable.

0 (DISABLED): Disable power to RAM 7 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

1 (ENABLED): Enable power to RAM 7 during sleep (4 kB addresses from 0x20000000 to 0x20000FFF).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data